**264 Part 3 The instruction-set processor level: variations in the processor **

**Section 5÷
** **Processors with stack memories (zero addresses per instruction)**

Fig. 1. Block diagram of the arithmetic unit. Full lines represent information transfers; dotted lines represent control pulses. All registers are 48-bits long unless otherwise stated.

made via W3. *W1 *and *W2, *together with B1 and *B2, *form a double-length shifting register which may be used as two independent single-length shifting registers.

B1 and *B2 *are the inputs to the 48-bit adder whose output may be routed to W1, W2, or to the characteristic difference register *CD.*

The adder contains 13 carry-skip stages which reduce the carry propagation time to a maximum of 150 nsec. Subtraction is performed by adding the minuend's complement to the subtrahend with a carry inserted into the right-most adder stage.

*Nb *acts as a buffer between store control and the arithmetic unit, and together with B1 and B2, is used in nearly every function.

Arithmetic unit control interprets each instruction as a sequence of timed pulses along lines which activate the various transfers etc., between the registers. The sequences have been constructed so that many operations are performed simultaneously, reducing the overall time to a minimum; thus the function *single-length fixed-point add *is performed by:

i Transferring *W1, W2, W3 *to *B2, *B1 and *Nb *respectively, simultaneously commencing a read from the nesting store, clearing the carry inserted into the right-most adder stage and switching the adder's output to W1.

*ii *Adding and simultaneously transferring *Nb *to W2.

Each step takes 0.5 m sec and by the end of the last step, W3 has been refilled from the core nesting store.

To speed up multiplication and division, these functions are carried out in a separate unit employing the stored carry principle, but the results are finally assimilated within the arithmetic unit.

A similar arithmetic unit operating only on single-length numbers could be designed using only four full-length registers. At least five registers are required to perform the function which interchanges the contents of the two most accessible cells in the nesting store with those of the next most accessible pair. The sixth register enables all double-length arithmetic operations to be performed without writing information back into the nesting during the function; this would have complicated the sequences and increased the time for the functions.

When determining the arrangement of transfer paths between the various registers, it** **was found sufficient to consider only the double-length functions which required complicated or lengthy sequences; in particular the function for adding two double-length floating numbers had great influence.

An overflow indication is set on fixed-point addition and subtraction if the sign of the result differs from that expected, and on floating-point operations if the characteristic exceeds the maximum allowable; shifting may also cause overflow.

Shift control

Shifting operations are effected by transfers between W1 (and/or *W2) *and B1 (and/or *B2), *and back again. The shift transfer paths from the *W *to the *B *registers provide right shifts of 0, 1, 2, 5